Generally, bipolar elements have a high driving ability for the amount of chip area occupied by the bipolar elements, and have a high accuracy in the processing of analog quantity. However, bipolar elements exhibit the disadvantages of a low integration density and a low input impedance. In contrast, MOS elements have a high input impedance and a high integration density, and accordingly it is effective to include MOS elements in a chip where bipolar elements are mainly used in order to supplement the disadvantages of the bipolar elements. As a typical example there are MOS top operational amplifiers where MOS elements are used at the input stage. These amplifiers are already being manufactured and sold.
In such a conventional BI-MOS integrated circuit device npn transistors are used as bipolar elements and p-channel MOS transistors are used as MOS elements. The method of producing such a BI-MOS integrated circuit device is described below with reference to FIG. 1.
At first as shown in FIG. 1(A), an n type high impurity density embedding layer 2 is produced on the p type silicon substrate 1, and thereafter, an n type low impurity density epitaxial layer 3 is grown thereon.
Thereafter, as shown in FIG. 1(B), a selective oxidization is conducted with an anti-oxidization film such as nitride film 4 as a mask, thereby producing thick oxide films 5 to electrically separate the element constituting regions 3a, 3b in the epitaxial layer 3.
Thereafter, as shown in FIG. 1(C), the silicon nitride films 4 are removed, silicon oxide films 6 are produced as protection films at the ion injection, and a photoresist film 7 is produced. Thereafter, boron ions are injected to the surface area of the semiconductor substrate through the oxide films 6 with the photoresist film 7 as a mask, and thereafter, the photoresist film 7 is removed, and the injected borons are driving-diffused by a thermal processing, thereby producing a base layer 8, a source layer 9, a drain layer 10 of all p types, and a diffusion resistance (not shown).
Thereafter, as shown in FIG. 1(D), an n type high impurity density (n.sup.+) collector contact layer 11 and an n.sup.+ emitter layer 12 are produced by an ion injection or a gas diffusion method.
And thereafter, as shown in FIG. 1(E), an oxide film 13, such as phosphite glass film, is deposited thereon, the portions of the oxide films 13 and 6 which portions are to become gates are both removed, and the gate oxide film 14 is produced again.
Finally, as shown in FIG. 1(F), contact holes are apertured to the oxide films 13 and 6 at the electrode leading regions, and the base electrode 15, emitter electrode 16, collector electrode 17, source electrode 18, gate electrode 19, and drain electrode 20, and other wirings are produced.
With respect to such BI-MOS integrated circuit devices, the requirements of high performance and high integration have become more severe. As shown in FIG. 2 which is a plan view of the device of FIG. 1(F), it is necessary to decrease the distance D between the one end of the contact hole 16a for the emitter electrode 16 which is a predetermined distance apart from the one end of the emitter (12)-base(8) junction and the one end of the contact hole 15a for the base electrode 15 in order to reduce the base resistance, and it is also necessary to decrease the area of the base layer 8 in order to reduce the base capacity. Furthermore, the integration density of MOS transistors in BI-MOS devices has become lower than that of the exclusive MOS element based on the overlapping of the gate oxide film 14 and the source/drain 9/10, and the increase of margin which is usually required caused by electrode wirings.
In manufacturing such an integrated circuit device it is an important problem to control the characteristic parameter of each element with high accuracy and high reproducibility. In BI-MOS integrated circuit devices the characteristic parameters which at least must be controlled are as follows:
(1) The junction resistivity of each element; PA1 (2) The amplification factor of the npn transistor (hFE) the amplification factor of the pnp transistor (hFE); and PA1 (3) The threshold voltage of the p-channel MOS transistor (Vth) PA1 (4) The resistance value of the diffusion resistance (R). PA1 (a) controlling the hFE at the n.sup.+ emitter diffusion process considering the variation of the hFE by a heating process conducted thereafter. PA1 (b) conducting only an n.sup.+ deposition at the n.sup.+ emitter diffusion process, and conducting a heating process in an inert ambient gas after all the heating processes required to produce MOS elements, including that for producing a gate oxide film, are conducted, thereby re-adjusting the value of hFE at the final process; and PA1 (c) conducting the processes which should be conducted after the n.sup.+ emitter diffusion, including those for producing the gate oxide film of the MOS elements, at a low temperature, thereby suppressing the variation of hFE to the smallest value.
As is apparent from the production process shown in FIG. 1, the heating process at an elevated temperature for producing gate oxide films must be executed after the n.sup.+ emitter diffusion process, and accordingly, the impurities in the n.sup.+ layer once diffused will be distributed again. Furthermore, it is quite difficult to control the amplification factor hFE of the npn transistor in the bipolar circuit portion with high accuracy, resulting in the biggest problem in the production process of BI-MOS integrated circuit device.
The following methods are considered for control the hFE of the npn transistor with high accuracy:
However, there are problems in all of these methods. For example, in the case of (a), the variations of the heating process to be conducted thereafter become large, making it difficult to predict the variation of the hFE with high reproducibility. In the case of (b), the variation of the Vth of the MOS element changes depending on the heating time in the heating process in an ambient inert gas. In the case of (c), it is difficult to control the energy level of the gate oxide film of the MOS element and that of the silicon substrate with high accuracy, thereby resulting in the instability of the Vth.